1. Field of the Invention
The present invention relates to an arithmetic unit, and more particularly, to a zero value detection circuit in the arithmetic unit, which determines if the result of any particular arithmetic operation is zero.
2. Description of the Related Art
The Arithmetic and Logic Unit (ALU) is one of the most important parts of a digital computer due to the computer's reliance on it to perform such instructed operations as add, complement, compare, shift, and move digital bits of data. A further function of the ALU is to determine when the result of an any particular arithmetic operation is zero. As the speed of processing digital information and the number of bits processed increase, it is also important to increase the operational speed of the ALU in determining whether the operational result of any given operation is zero or not.
FIG. 1 illustrates one of a variety of conventional ALUs incorporated in a computer's Central Processing Unit (CPU). This arithmetic unit comprises a combinational circuit 32, a zero value detector 33 for determining if the operation result of the combinational circuit 32 is zero, and a zero flag register 34. The combinational circuit 32 receives a first binary number "A" consisting of bits A1 to A8 (A8: most significant bit) and a second binary number "B" consisting of bits B1 to B8 (B8: most significant bit). The circuit 32 then performs an addition or other logical operation on the individual bits binary numbers A and B, and outputs the operational result "C" consisting of bits C1 to C8 (C8: most significant bit). The zero detector 33 receives the bits C1 to C8 and determines if this operation result C is zero or not.
The zero value detector 33 as shown in more detail in FIG. 2 includes four double-input NOR gates 351 to 354 and a four input single output AND gate 36. The output of each NOR gate 351-354 goes high, (i.e., gets set to "1") only when the two inputs associated with each gate C1-C2 to C7-C8 respectively are set low, (i.e., set to "0"). The output of the AND gate 36 goes high and is stored in the zero flag register 34 only when the output at each NOR gate 351 to 354 is high.
As is typical with many conventional ALUs, after the combinational circuit 32 completes an arithmetic operation, the zero detector 33 executes zero detection based on the result of the operation. Conventional ALUs also have the ability to process multi-bit data such as 16-bit or 32-bit data. With larger amounts of data, however, the combinational circuit 32 inevitably requires longer periods of time to complete its operation. This, in turn, effectively increases the time the ALU takes to perform zero detection for any given operation. Moreover, should the flag for the zero flag register 34 not be properly set when the CPU refers to the zero flag register 34, the CPU will malfunction. consequently, the operational speed of the CPU is directly influenced by the zero value detection operation of the ALU. This CPU/ALU relationship has in the past hindered improving the operational speed of the CPU.